RVA23 Extension Software Stack Matrix

Which software layer needs to change to support each RVA23 extension?

Why RVA23 matters — the ISA milestones at a glance

RVA23 is the release where the RISC-V Application Profile reaches Armv8.0–v8.4 baseline parity for phones and servers. Inside the ISA profile itself, the headline upgrades are:

Vector (V) becomes mandatory in U64 — every conformant chip ships RVV 1.0. SIMD is no longer optional. New in RVA23.
Hypervisor (H) becomes mandatory in S64 via the Sha umbrella — KVM-RISCV, pKVM, Android protected VMs. Was optional in RVA22S64. The biggest single change for system silicon.
Vector-crypto base mandatory: Zvbb + Zvkt (vector bit-manipulation + data-independent timing). AES-GCM via optional Zvkng / SM4-GCM via Zvksg. Closes the ~13-year gap to Arm's AESE/AESD/PMULL.
Pointer masking (Supm) mandatory in U64 — tagged-pointer ABI for HWASan, GC-style runtimes, plus parity with Arm TBI / MTE's userspace control surface.
Scalar quality-of-life: Zicond (conditional move), Zfa (FP additions / immediate loads), Zicboz + Zicbom (cache-block ops), Zawrs (low-power spin) — closes long-standing scalar performance gaps with Arm and x86.

Several adjacent features that vendors typically bundle with "RVA23-class" products are not in the ISA profile and so do not appear in the U64 / S64 matrix — in particular AIA (see the dedicated AIA tab for Smaia/Ssaia/IMSIC/APLIC breakdown), IOMMU, RAS, ACPI / DT bindings, SBI v2.0+. See also the Platform-layer items not covered block at the bottom.

Arch. state class — does this extension add architectural state? (5-way refinement)

Cross-cutting with the software-layer view: which extensions add architectural state — registers or CSRs the OS must save/restore on context switch? The primary axis is binary (with vs without), grounded in the RISC-V Privileged Architecture spec's own state-tracking machinery (mstatus.FS, mstatus.VS) and the Smstateen/Ssstateen mechanism. The without side splits further into instruction-additions vs pure capability advertisements.

State class	Examples	Spec basis
Without architectural state — no OS save/restore needed
insn-only	`M`, `A`, `C`, `B`, `Zba`, `Zbb`, `Zbs`, `Zcb`, `Zicond`, `Zicbom`, `Zicboz`, `Zihintpause`, `Zawrs`, `Svinval`, `Zifencei`, `Zacas`, `Zabha`, `Zbc`…	Adds new instructions that compute on existing GPRs / memory. No new persistent state. Bitmanip rationale (B): "do not add any new architectural state." Same logic for HINTs, CMOs, atomics, fence variants.
property	`Zic64b`, `Za64rs`, `Za128rs`, `Ziccamoa`, `Ziccif`, `Zicclsm`, `Ziccrse`, `Zkt`, `Sv39`, `Sv48`, `Sv57`, `Svnapot`, `Svpbmt`, `Svade`, `Svadu`…	Named-feature / capability extensions — assert one architectural guarantee (cache geometry, atomicity rule, page-table mode value, timing property…) and add neither instructions nor state. Pure discoverable bits; `hwprobe(2)` reports them as flags, not feature tests.
With architectural state — OS must save/restore on context switch
fp	`F`, `D`, `Zfh`, `Zfhmin`, `Zfa`, `Zfbfmin`	`mstatus.FS` (Priv Arch §3.1.6 — "Floating-point context Status"). FPU register file `f0–f31` + `fcsr`; spec rationale: "using dirty bits on floating-point register file state can reduce context-switch overhead."
vector	`V`, `Zvbb`, `Zvfh`, `Zvfhmin`, `Zvkng`, `Zvkt`…	`mstatus.VS` (Priv Arch §3.1.6 — "Vector context Status"). Vector register file `v0–v31` + `vstart`, `vl`, `vtype`, `vxrm`, `vxsat`, `vcsr`.
csr-only	`H`, `Ss1p13`, `Sstc`, `Ssaia`, `Supm`, `Ssstateen`, `Sdtrig`, `Sscofpmf`, `Zicfilp`, `Zicfiss`, `Zkr`	Per-extension new CSR(s) or new bits in existing CSRs — no new wide register file. Many require an `{m,h,s}stateen0..3` enable bit (`Smstateen`/`Ssstateen` spec §3) or have their own access-gating bit in `menvcfg`/`senvcfg`.

The 5-way scheme is an engineering refinement — not normative spec terminology. The binary split (with / without state) is anchored in mstatus.FS/VS and Smstateen; the further insn-only vs property split has no single canonical name but matches the operational reality: property extensions are invisible to compilers and userspace, only observable via discovery (e.g. Linux hwprobe). State class is orthogonal to the "Layer" column — e.g. F is fp but software-layer full-stack; Zicbom is insn-only but software-layer kernel. Hover any state tag in the table below to see its individual spec citation.

None (transparent)

Compiler

Kernel

Userspace libs

Full stack

Filter layer: Mandatory only New in RVA23 only

Filter arch. state:

Spec: RISC-V Advanced Interrupt Architecture v1.0 (PDF) · Source: riscv/riscv-aia · Ratified: 2023-07-01
This tab inventories what the AIA v1.0 specification defines. Content is restricted to what the spec itself states; no editorial commentary on schedule or future profiles.

ISA-level extensions — hart-resident, indexed by UDB

Smaia
Machine-mode AIA. AIA spec defines new M-level CSRs: miselect, mireg, mtopei, mtopi, mvien, mvip, midelegh, mieh, miph. UDB: spec/std/isa/ext/Smaia.yaml · ratified 2023-07-01.
Ssaia
Supervisor-mode AIA. AIA spec defines new S-level CSRs: siselect, sireg, stopei, stopi, sieh, siph. With H: hvien, hvictl, hviprio1, hviprio2, vsiselect, vsireg, vstopei, vstopi, vsieh, vsiph. Requires S ≥ 1.12. UDB: spec/std/isa/ext/Ssaia.yaml · ratified 2023-07-01.
Smcsrind / Sscsrind
Indirect CSR access mechanism (m/siselect + m/sireg*). UDB places miselect and siselect under the Smcsrind directory; AIA uses this window to expose its CSRs. UDB: spec/std/isa/ext/Smcsrind.yaml / Sscsrind.yaml.

Hardware components — defined by the AIA spec, not ISA extensions

IMSIC
Incoming MSI Controller. Per-hart memory-mapped block. AIA spec specifies one interrupt file per privilege level (M, S, and one per VS guest under H). Devices deliver interrupts by writing to a hart's IMSIC; the corresponding *topei CSR reports the highest-priority pending identity. Spec: AIA v1.0 chapters 3 (IMSIC) and 6 (interrupts for virtual machines).
APLIC
Advanced Platform-Level Interrupt Controller. AIA spec defines two delivery modes: direct delivery (interrupt asserted to a hart as an external interrupt) and MSI delivery (interrupt converted into an MSI write targeted at an IMSIC). A system may contain multiple APLICs in a hierarchy. Spec: AIA v1.0 chapters 4 (APLIC) and 5 (duties of machine-mode software).

Related extensions referenced by the AIA spec

Ssstateen / Smstateen
The state-enable CSRs include an AIA bit (*stateen0.AIA) controlling lower-privilege access to AIA state. Mandatory in RVA23S64. UDB: spec/std/isa/ext/Ssstateen.yaml / Smstateen.yaml · RVA23S64.yaml lists Ssstateen as mandatory.
H
AIA spec chapter 6 defines per-VS-guest IMSIC interrupt files and the hvien / hvictl / hviprio* CSR set, all gated by the hypervisor extension. Mandatory in RVA23S64 (via the Sha umbrella). UDB: spec/std/isa/ext/H.yaml.
S ≥ 1.12
Ssaia declares this as its required Supervisor version. The Supervisor v1.13 update (in RVA23S64 as Ss1p13) is a superset. UDB: spec/std/isa/ext/Ssaia.yaml requirements.extension.name: S.

Status in RVA profiles

Smaia and Ssaia do not appear in the mandatory or non-mandatory extension lists of RVA20, RVA22, or RVA23 (U64 or S64).
Server Platform v1.0 (riscv-non-isa/riscv-server-platform) mandates Ssaia under rule RVA_020 and APLIC under the hardware rules. See the Server Platform v1.0 tab. The Server Platform spec itself notes: "These mandates may be moved into a new ISA profile specification."

Spec: riscv-server-platform.pdf v1.0 · Source: riscv-non-isa/riscv-server-platform · requirements.adoc

RVA23S64   (78 mandatory ISA extensions, fully inherited via RVA_010)
    │
    └──► Server Platform Spec v1.0 adds on top:
         ├─ MUST     RVA_020          Sv48, Sdtrig, Sdext, Zkr, Ssccfg, Ssstrict, Ssaia   (7 ISA exts)
         ├─ SHOULD   RVA_030 / 040    Svadu, Ssctr                                        (2 recommended ISA)
         ├─ MUST     FIRM_020 / 030   SBI v3.0 DBTR  ·  conditional: SBI v3.0 SSE          (firmware ABI)
         ├─ MUST     HSOC / HPER / FIRM_140   APLIC, IOMMU, Server SoC v1.0, TPM 2.0, UART, ...   (platform HW)
         └─ MUST     SEC_010..110     UEFI Secure Boot, hardware RoT, signed FW updates   (security)

ISA extensions added on top of RVA23S64 — Server Platform Hardware Rules § RISC-V Harts

RVA_020 MUST7 mandatory ISA additions

Sv48
48-bit virtual addressing. RVA23S64: optional → promoted to MUST.
Sdtrig
Debug triggers. SEE_020 further mandates ≥4 instruction-address and ≥4 load/store-address match triggers. RVA23S64: optional → promoted to MUST.
Sdext
External debug extension. NEW — not in RVA23S64.
Zkr
Entropy-source CSR (seed) — servers need entropy at boot. RVA23S64: optional → promoted to MUST.
Ssccfg
Counter configuration extension. NEW — not in RVA23S64.
Ssstrict
Implementation must not include non-standard extensions or use reserved encodings. RVA23S64: optional → promoted to MUST.
Ssaia
S-mode part of the Advanced Interrupt Architecture — the ISA-level CSRs paired with platform-level APLIC/IMSIC. This is the "AIA piece" that RVA23 itself does not require. NEW — not in RVA23S64. Spec note: "These mandates may be moved into a new ISA profile specification."

RVA_030 / 040 SHOULD2 recommended ISA additions

Svadu
Hardware A/D-bit updating in page-table entries. RVA23S64: optional → still optional. "Expected to become mandatory in a future version."
Ssctr
Control Transfer Records. If implemented, a CTR depth of 32 is mandatory (uniform depth aids VM migration; useful for profile-guided optimisation). NEW — not in RVA23S64. "Expected to become mandatory in a future version."

RVA_060 MUSTSizing constraint on an already-mandatory extension

Zihpm ≥ 6
At least 6 hardware performance counters, on top of the three defined by Zicntr. Not a new extension — a minimum-instance count on one RVA23 already mandates.

Firmware / SBI — Server Platform Firmware Rules

FIRM_010 MUSTBRS-I recipe from Boot & Runtime Services v1.0
FIRM_020 MUSTSBI v3.0 DBTR (Debug Triggers) — required so S-mode can drive Sdtrig
FIRM_030 if-RASSBI v3.0 SSE (Supervisor Software Events) — required when any RISC-V RAS support is present
FIRM_140 MUSTIOMMU described via RIMT ACPI table
FIRM_150..170Forward-edge CFI in UEFI runtime services (signaled via EFI memory-attribute flag; entry must be lpad 0)

Platform hardware — SoC, peripherals, interrupt controller, IOMMU

HSOC_010 MUSTSoC complies with Server SoC v1.0 (a separate spec)
HSOC_020 MUSTVM-assignable / userspace-driver peripherals must be PCIe (or SoC-integrated PCIe). APLIC, IOMMU, debug, RoT explicitly excluded.
implicitInterrupt controller (typically APLIC per the AIA spec) — required via Ssaia + HSOC rules
implicitIOMMU per the RISC-V IOMMU spec — required for PCIe device assignment to VMs
HPER_010 MUST16550- or PL011-compatible UART (115200 baud, flow control, IRQ-driven)
HPER_030..040If USB present: XHCI 1.2+; if SATA present: AHCI 1.3.1+ (both with 64-bit addressing)
HPER_070 MUSTBattery-backed RTC for UEFI certificate validity
HPER_090 MUSTTPM 2.0 (TPM 2.0 Library spec)

Security — Server Platform Security Rules

SEC_010 MUSTHardware Root of Trust, isolated from the application processor (examples: OpenTitan, Caliptra)
SEC_020 MUSTRoT manages a security lifecycle: Manufacture → Provisioning → Secured → Recoverable Debug → Terminated
SEC_030 SHOULDRoT-rooted secure identity + platform attestation (TCG DICE / SPDM)
SEC_040 MUSTUEFI Secure Boot + driver signing
SEC_080..100 MUSTIn-band firmware updates with signed payloads + signature validation before applying

Structural summary only. For exact rule wording, cite references, and conformance details, read the source server_platform_requirements.adoc.

Mandatory Extensions

Extension	Description	Instructions?	CSRs?	Arch. state	GCC march	LLVM march	Linux kernel	Layer	Notes

Optional Extensions

Extension	Description	Instructions?	CSRs?	Arch. state	GCC march	LLVM march	Linux kernel	Layer	Notes

Platform-layer items not covered: RVA23 is a CPU-ISA-only profile. The following components are required by RISC-V platform specs (Server Platform, BRS / EBBR / SBBR) but are not part of any RVA profile and so do not appear in this matrix. For a structured view of what the server platform spec adds on top of RVA23, see the Server Platform v1.0 tab above.

IOMMU — DMA address translation. Spec: RISC-V IOMMU Architecture Specification (ratified 2024). Reuses CPU PTE formats (Sv39x4 / Sv48x4 / Sv57x4) and inter-operates with H-extension G-stage translation. Linux: drivers/iommu/riscv/ (v6.13+).
AIA / IMSIC / APLIC — Advanced Interrupt Architecture. Specs: Ssaia / Smaia extensions, optional and not listed in RVA23. Linux: drivers/irqchip/irq-riscv-{imsic,aplic}-*.c.
RAS — Reliability / Availability / Serviceability. Spec: RERI (RISC-V Error Reporting Interface).
ACPI / Device Tree bindings — Extension discovery via ACPI RHCT or DT riscv,isa-extensions; SBI capability probing.
Firmware interfaces — SBI (Supervisor Binary Interface) versions, UEFI requirements (SBBR-RV / EBBR-RV), secure-boot chain.