{ "_metadata": { "description": "RVA23U64 Extension Software Stack Coverage Matrix", "last_updated": "2026-05-12", "gcc_source": "https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html (GCC trunk, 2026-05)", "llvm_source": "https://llvm.org/docs/RISCVUsage.html (LLVM 23.0.0git, 2026-05)", "kernel_source": "linux-kernel-coverage.html (Linux 7.0-rc1)", "udb_source": "riscv-unified-db spec/std/isa/profile/RVA23U64.yaml (inheritance chain: RVA20U64 -> RVA22U64 -> RVB23U64 -> RVA23U64)", "editorial_note": "Sub-extensions implicitly required by a mandatory umbrella extension are omitted: Zaamo/Zalrsc (subsets of A); Zca/Zcd (subsets of C); Zve32f, Zve32x, Zve64d, Zve64f, Zve64x, Zvl32b, Zvl64b, Zvl128b (subsets of V); Zvkb (implied by Zvbb). They appear in the UDB-generated cfg flat list but do not drive distinct software-stack work beyond their umbrella. Zcf is similarly a sub-component of compressed FP and is not separately optional in the profile source.", "layer_definitions": { "none": "No new instructions. Platform property guarantee only - hardware must meet this constraint, but software (compiler, kernel, userspace) needs no changes.", "compiler": "Has ISA instructions that the compiler can auto-generate when -march enables the extension. No kernel or userspace library changes needed.", "kernel": "Requires kernel changes (e.g., page table semantics, signal handling, perf subsystem). Userspace is largely transparent.", "userspace": "Requires userspace runtime library changes (glibc, OpenSSL, etc.) beyond what the compiler provides.", "full_stack": "Impacts the entire stack: kernel, compiler, and userspace libraries all need changes." } }, "mandatory": [ { "name": "I", "long_name": "Base Integer", "description": "Base 64-bit integer instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (part of 'g' or explicit 'i')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "Base ISA, always present.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Base ISA — defines GPR file and integer instruction set (baseline, not extension-added)" }, { "name": "M", "long_name": "Integer Multiply/Divide", "description": "Hardware integer multiplication and division", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (part of 'g')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler generates MUL/DIV. No kernel/userspace changes needed.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "ISA Manual §M — multiply/divide instructions, no new register" }, { "name": "A", "long_name": "Atomic", "description": "Load-reserved/store-conditional and atomic memory operations", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (part of 'g')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "userspace", "layer_note": "glibc pthread/futex implementations use LR/SC and AMOs directly.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "ISA Manual §A — LR/SC and AMO instructions; reservation set is microarch, no new register" }, { "name": "F", "long_name": "Single-Precision Float", "description": "32-bit IEEE 754 floating-point", "has_instructions": true, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported (part of 'g')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Compiler generates FP instructions; kernel saves/restores FP state in signal handling; glibc FP ABI.", "rva23_new": false, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status)" }, { "name": "D", "long_name": "Double-Precision Float", "description": "64-bit IEEE 754 floating-point", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (part of 'g')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Same as F but for 64-bit. Signal frame, ptrace, glibc ABI all affected.", "rva23_new": false, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status)" }, { "name": "C", "long_name": "Compressed", "description": "16-bit compressed instruction encoding", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (part of 'g')", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler emits C instructions automatically when enabled. Kernel jump labels handle mixed 16/32-bit.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "ISA Manual §C — alternative compressed encodings of existing instructions" }, { "name": "B", "long_name": "Bit Manipulation", "description": "Shorthand for Zba+Zbb+Zbs", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler auto-generates bit manipulation instructions. No kernel/userspace changes needed.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Bitmanip rationale: extension adds new instructions, no new architectural state (umbrella for Zba+Zbb+Zbs)" }, { "name": "U", "long_name": "User Mode", "description": "User-mode privilege specification", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Implicit in base ISA", "llvm_march": true, "llvm_status": "Implicit in base ISA", "linux_kernel": true, "layer": "none", "layer_note": "Privilege architecture. Defines U-mode. Software implication: trap handling, syscall convention.", "rva23_new": false, "state_class": "property", "state_class_basis": "User privilege mode — discoverable capability; mstatus has U-mode bits in base" }, { "name": "V", "long_name": "Vector 1.0", "description": "SIMD vector extension with configurable register width", "has_instructions": true, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Heaviest extension for distro adoption. Kernel: sigcontext vector state save/restore, ptrace, fork/exec. Userspace: glibc vector ABI, OpenSSL/libc optimized routines. Heterogeneous VLEN on SMP is rejected by kernel.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status); adds v0–v31, vstart, vl, vtype, vxrm, vxsat, vcsr" }, { "name": "Supm", "long_name": "User-mode Pointer Masking", "description": "Pointer masking available in user mode (per UDB: 'execution environment' announcement; the underlying CSR control lives in Smnpm/Ssnpm)", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Kernel side: configures S/Smnpm/Ssnpm CSR fields, exposes opt-in to userspace via prctl(PR_SET_TAGGED_ADDR_CTRL) (mirroring Arm TBI/MTE), saves/restores PMLEN across context switch, plumbs ptrace. Userspace side: pointer-tagging libraries (HWASan, MTE-style allocators, GC-style runtimes) consume tagged pointers; glibc must honor the masked-pointer ABI on syscalls. Analogous to Arm's TBI/MTE, which is universally treated as full-stack rather than kernel-only.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "menvcfg.PMM / senvcfg.PMM (Pointer Masking spec §3)" }, { "name": "Za64rs", "long_name": "Reservation Set ≤64B", "description": "Reservation sets contiguous, aligned, ≤64 bytes", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Software-transparent hardware constraint on LR/SC reservation granularity.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (reservation-set size ≥64 B)" }, { "name": "Za128rs", "long_name": "Reservation Set ≤128B", "description": "Reservation sets contiguous, aligned, ≤128 bytes", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Relaxes Za64rs constraint.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (reservation-set size ≤128 B)" }, { "name": "Zawrs", "long_name": "Wait on Reservation Set", "description": "WRS.STO / WRS.NTO instructions for low-power polling loops", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Assembly Support", "linux_kernel": true, "layer": "userspace", "layer_note": "glibc futex implementation can use WRS for efficient waiting. LLVM only has assembly support (no pattern matching).", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "ISA Manual §Zawrs — wrs.{nto,sto} instructions, no new state" }, { "name": "Zba", "long_name": "Address Calculation", "description": "Address generation instructions (sh1add, sh2add, sh3add, etc.)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler auto-generates for address calculations. Transparent to kernel/userspace.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Bitmanip rationale: extension adds new instructions, no new architectural state" }, { "name": "Zbb", "long_name": "Basic Bit Manipulation", "description": "Count leading/trailing zeros, bit reverse, or-combine, etc.", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler pattern-matches idioms (e.g., __builtin_ctz → ctz). Transparent.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Bitmanip rationale: extension adds new instructions, no new architectural state" }, { "name": "Zbs", "long_name": "Single-Bit Operations", "description": "Bit manipulation on single bits (bset, bclr, binv, bext)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler auto-generates. Transparent.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Bitmanip rationale: extension adds new instructions, no new architectural state" }, { "name": "Zcb", "long_name": "Code Size Reduction", "description": "Simple 16-bit compressed instructions for code size savings", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler auto-generates C-extension alternatives for common instructions. Pure code-size optimization.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "Zc rationale — additional compressed encodings, no new state" }, { "name": "Zcmop", "long_name": "Compressed May-Be-Operations", "description": "8 reserved 16-bit encodings for future MOP redefinition", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "Currently defined as NOPs (write zero to x[rd]). Reserved for future redefinition. No functional impact today.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "Zcmop — c.mop.n reserves compressed encodings (HINT-class), no new state" }, { "name": "Zimop", "long_name": "May-Be-Operations", "description": "32-bit encodings reserved for future instruction redefinition", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "Currently defined as NOPs. Reserved for future redefinition. No functional impact today.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "Zimop — MOP.r/MOP.rr reserve encodings (HINT-class), no new state" }, { "name": "Zfa", "long_name": "Additional Floating-Point", "description": "FP immediate loads, fmin/fmax, round-to-int, quiet comparisons, etc.", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler auto-generates new FP instructions. No new state to save/restore.", "rva23_new": true, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status) (extends F/D operations)" }, { "name": "Zfhmin", "long_name": "Minimal Half-Precision Float", "description": "Minimal IEEE 754 half-precision: load/store and conversions to/from single (and double if D present)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler emits flh/fsh/fmv.x.h/fmv.h.x/fcvt.{s,d}.h/fcvt.h.{s,d} when -march enables Zfhmin. Uses existing F-register file: no new architectural state, so no kernel signal-frame or glibc ABI changes beyond what F already requires.", "rva23_new": false, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status) (half-precision subset)" }, { "name": "Zic64b", "long_name": "64-Byte Cache Block", "description": "Cache blocks must be 64 bytes, naturally aligned", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "Platform property. No new instructions. Kernel: L1_CACHE_BYTES, DMA alignment, data structure layout. Device Tree provides cache block sizes.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (cache-block size = 64 B)" }, { "name": "Zicbom", "long_name": "Cache Block Management", "description": "CBO.CLEAN / CBO.FLUSH / CBO.INVAL instructions", "has_instructions": true, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Assembly Support", "linux_kernel": true, "layer": "kernel", "layer_note": "Kernel uses for cache management (DMA ops, page table maintenance). LLVM only has assembly support. Userspace can use via __builtin_riscv_cache_* but mainly kernel concern.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "CMO spec — CBO.* management instructions; menvcfg.CBCFE/CBIE gates only" }, { "name": "Zicbop", "long_name": "Cache Block Prefetch", "description": "PREFETCH.R / PREFETCH.W / PREFETCH.I instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler can auto-generate prefetch instructions. Also usable via __builtin_prefetch. Transparent to kernel.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "CMO spec — CBO.PREFETCH.* are HINT instructions, no new state" }, { "name": "Zicboz", "long_name": "Cache Block Zero", "description": "CBO.ZERO instruction for zeroing cache blocks", "has_instructions": true, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Assembly Support", "linux_kernel": true, "layer": "full_stack", "layer_note": "Kernel uses cbo.zero for fast page clearing AND must set senvcfg.CBZE to authorize U-mode execution (cbo.zero traps as illegal in U-mode while the bit is 0). Once enabled, userspace runtime (glibc memset, libc clear primitives) can issue cbo.zero directly. LLVM has assembly support only - no auto-generation. Linux exposes the capability via the riscv_hwprobe vDSO/syscall (block size in RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE).", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "CMO spec — CBO.ZERO instruction; menvcfg.CBZE gate only, no new state" }, { "name": "Ziccamoa", "long_name": "Memory Supports All Atomics", "description": "Cacheable coherent memory must support all A-extension AMOs", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Software-transparent hardware memory system constraint.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (AMO atomicity rule)" }, { "name": "Ziccif", "long_name": "Atomic Instruction Fetch", "description": "Instruction fetches of aligned power-of-2 sizes are atomic", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Software-transparent.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (instruction-fetch coherence guarantee)" }, { "name": "Zicclsm", "long_name": "Misaligned Load/Store Support", "description": "Misaligned loads/stores to cacheable coherent memory must work", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Note: misaligned may be extremely slow - software should not rely on it for performance.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (misaligned load/store support guarantee)" }, { "name": "Ziccrse", "long_name": "LR/SC Forward Progress", "description": "Memory system guarantees forward progress on LR/SC sequences", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Software-transparent.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (reservation-set eventual success guarantee)" }, { "name": "Zicntr", "long_name": "Base Counters and Timers", "description": "CYCLE, TIME, and INSTRET CSRs", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (unconditionally accepted)", "linux_kernel": true, "layer": "none", "layer_note": "No new instructions. CSRs for performance counters. LLVM accepts unconditionally for backward compat.", "rva23_new": false, "state_class": "csr-only", "state_class_basis": "Unprivileged counter CSRs cycle/time/instret (URO)" }, { "name": "Zicond", "long_name": "Conditional Operations", "description": "CZERO.EQZ / CZERO.NEZ conditional select instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "Compiler pattern-matches conditional idioms and generates CZERO. Transparent.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "Zicond — czero.{eqz,nez} conditional-move instructions, no new state" }, { "name": "Zicsr", "long_name": "CSR Access", "description": "CSRRW/CSRRS/CSRRC/CSRRWI/CSRRSI/CSRRCI instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (unconditionally accepted)", "linux_kernel": true, "layer": "none", "layer_note": "CSR access instructions. LLVM accepts unconditionally for backward compat.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Zicsr defines CSR access instructions; the CSRs themselves belong to other extensions" }, { "name": "Zihintntl", "long_name": "Non-Temporal Locality Hints", "description": "HINT.NTL.P1/PALL/S1/SALL hint instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "Hint instructions - architecture-defined NOPs. Hardware may use for cache policy hints. Software-transparent.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "HINT-class encoding — software-transparent additions to existing instruction space, no new state" }, { "name": "Zihintpause", "long_name": "Pause Hint", "description": "PAUSE hint instruction for spin-wait loops", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Assembly Support", "linux_kernel": true, "layer": "userspace", "layer_note": "glibc spinlocks and futex can use PAUSE for efficient spinning. LLVM only has assembly support.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "HINT-class encoding — software-transparent additions to existing instruction space, no new state" }, { "name": "Zihpm", "long_name": "Hardware Performance Monitor", "description": "Hardware performance counter CSRs (hpmcounter3..31, etc.)", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (unconditionally accepted)", "linux_kernel": true, "layer": "kernel", "layer_note": "No new instructions. Kernel perf subsystem needs to expose hpmcounter CSRs to userspace via perf_events.", "rva23_new": false, "state_class": "csr-only", "state_class_basis": "hpmcounter3..31 / mhpmcounter3..31 / mhpmevent3..31 (Priv Arch §3.1.11)" }, { "name": "Zkt", "long_name": "Constant-Time Execution", "description": "Attests data-independent execution time for a safe instruction subset", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "No new instructions. Hardware property guarantee for cryptographic constant-time. Software-transparent.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (data-independent execution latency)" }, { "name": "Zvbb", "long_name": "Vector Bit Manipulation", "description": "Vector versions of Zbb instructions (vrol, vror, vbrev, etc.)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Requires V extension. Compiler can generate; kernel must handle in V sigcontext. Crypto libraries benefit.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector bit-manipulation)" }, { "name": "Zvfhmin", "long_name": "Vector Minimal Half-Precision", "description": "Vector conversions between half and single precision", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Requires V extension. Adds vfwcvt.f.f.v and vfwcvt.f.x.v. No new register state beyond V.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector FP16 subset)" }, { "name": "Zvkt", "long_name": "Vector Constant-Time", "description": "Vector instructions must execute with data-independent latency", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "none", "layer_note": "No new instructions. Hardware property guarantee for vector crypto constant-time. Software-transparent.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector data-independent timing — capability over vector state)" } ], "optional": [ { "name": "Zabha", "long_name": "Atomic Byte/Halfword", "description": "AMOSWAP.B, AMOSWAP.H, AMOADD.B, AMOADD.H instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "userspace", "layer_note": "glibc pthread can use for byte/halfword atomic ops. Kernel futex optimization.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "ISA Manual §Zabha — byte/halfword AMO instructions, no new register" }, { "name": "Zacas", "long_name": "Atomic Compare-and-Swap", "description": "AMOCAS.W/D/Q compare-and-swap instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (no amocas.q on RV64 due to ABI)", "linux_kernel": true, "layer": "userspace", "layer_note": "glibc pthread and lock-free data structures benefit. LLVM won't generate amocas.q on RV64 (ABI compat).", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "ISA Manual §Zacas — amocas.{w,d,q} instructions, no new register" }, { "name": "Zama16b", "long_name": "16B-Atomic Misaligned Access", "description": "Misaligned AMOs within 16B boundary are atomic", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": false, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Not yet in Linux kernel cpufeature.", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (misaligned access atomicity ≤16 B)" }, { "name": "Zbc", "long_name": "Carry-Less Multiplication", "description": "CLMUL/CLMULH carry-less multiply instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "userspace", "layer_note": "Used by CRC and crypto libraries. Compiler intrinsics; no auto-generation.", "rva23_new": true, "state_class": "insn-only", "state_class_basis": "Bitmanip rationale: extension adds new instructions, no new architectural state (carry-less multiply)" }, { "name": "Zfbfmin", "long_name": "Minimal BF16 Support", "description": "BF16 conversions and loads", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "compiler", "layer_note": "ML/AI workloads. Compiler can generate BF16 conversion instructions.", "rva23_new": true, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status) (bf16↔f32 conversion)" }, { "name": "Zfh", "long_name": "Half-Precision Float", "description": "Full half-precision floating-point (arithmetic + convert)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Superset of Zfhmin. Adds FP16 arithmetic. Compiler generates; kernel saves FP16 state in signal frame.", "rva23_new": false, "state_class": "fp", "state_class_basis": "mstatus.FS (Priv Arch §3.1.6 — Floating-point context Status) (half-precision FP)" }, { "name": "Ziccamoc", "long_name": "Memory Supports Casual AMOs", "description": "Cacheable coherent memory supports non-arithmetic AMOs", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": false, "layer": "none", "layer_note": "Platform property guarantee. No new instructions. Not yet in Linux kernel.", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (AMO ordering with sequence)" }, { "name": "Zicfilp", "long_name": "Landing Pad (CFI)", "description": "Indirect branch tracking via landing pad labels", "has_instructions": true, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Experimental (experimental-zicfilp)", "linux_kernel": true, "layer": "full_stack", "layer_note": "Compiler generates shadow landing pads; kernel manages enforcement state; ELF binary format changes; distro must handle mixed CFI/non-CFI binaries. LLVM still experimental.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "Forward CFI: elp tracking + mstatus.SPELP/MPELP, menvcfg.LPE/henvcfg.LPE/senvcfg.LPE (Zicfilp spec)" }, { "name": "Zicfiss", "long_name": "Shadow Stack (CFI)", "description": "Hardware shadow stack for return address protection", "has_instructions": true, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Experimental (experimental-zicfiss)", "linux_kernel": true, "layer": "full_stack", "layer_note": "Kernel manages shadow stack memory; signal handling must save/restore SSP; ptrace needs new regset; glibc must be compiled with shadow stack support. LLVM still experimental.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "Shadow stack: ssp CSR + menvcfg.SSE/henvcfg.SSE/senvcfg.SSE (Zicfiss spec)" }, { "name": "Zvbc", "long_name": "Vector Carryless Multiply", "description": "Vector CLMUL for cryptography (GHASH, CRC, ECC)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (intrinsics only)", "linux_kernel": true, "layer": "userspace", "layer_note": "OpenSSL/GnuTLS acceleration. Compiler intrinsics only (no pattern matching in GCC or LLVM). Requires V.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector carry-less multiply)" }, { "name": "Zvfbfmin", "long_name": "Vector BF16 Converts", "description": "Vector conversions to/from BF16", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "ML/AI vector workloads. Requires V. No new register state.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector bf16↔f32 conversion)" }, { "name": "Zvfbfwma", "long_name": "Vector BF16 Widening Multiply-Add", "description": "Vector BF16 widening multiply-add instructions", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "ML/AI vector workloads. Requires V + Zvfbfmin. No new register state.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector bf16 widening FMA)" }, { "name": "Zvfh", "long_name": "Vector Half-Precision Float", "description": "Full vector half-precision floating-point", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "full_stack", "layer_note": "Superset of Zvfhmin. Adds vector FP16 arithmetic. Requires V.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector half-precision FP)" }, { "name": "Zvkng", "long_name": "Vector NIST Crypto (GCM)", "description": "Shorthand for Zvkn + Zvkg (NIST suite + GCM)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (intrinsics only)", "linux_kernel": true, "layer": "userspace", "layer_note": "OpenSSL/GnuTLS AES-GCM acceleration. Compiler intrinsics only. Requires V.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector NIST crypto bundle: Zvkn+Zvkg)" }, { "name": "Zvksg", "long_name": "Vector ShangMi Crypto (GCM)", "description": "Shorthand for Zvks + Zvkg (SM suite + GCM)", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported (intrinsics only)", "linux_kernel": true, "layer": "userspace", "layer_note": "OpenSSL/GnuTLS SM4-GCM acceleration. Compiler intrinsics only. Requires V.", "rva23_new": true, "state_class": "vector", "state_class_basis": "mstatus.VS (Priv Arch §3.1.6 — Vector context Status) (vector ShangMi crypto bundle: Zvks+Zvkg)" } ], "summary": { "mandatory_count": 39, "optional_count": 15, "by_layer": { "none": "Platform property or NOP - software-transparent", "compiler": "Compiler auto-generates - march enables, no other changes", "kernel": "Kernel adaptation needed - userspace largely transparent", "userspace": "Userspace libraries (glibc, OpenSSL) need adaptation", "full_stack": "Kernel + compiler + userspace libraries all need work" } } }