{ "_metadata": { "description": "RVA23S64 Extension Software Stack Coverage Matrix (supervisor-mode profile additions)", "last_updated": "2026-05-12", "gcc_source": "https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html (GCC trunk, 2026-05)", "llvm_source": "https://llvm.org/docs/RISCVUsage.html (LLVM 23.0.0git, 2026-05)", "kernel_source": "linux-kernel-coverage.html (Linux 7.0-rc1)", "udb_source": "riscv-unified-db spec/std/isa/profile/RVA23S64.yaml (inherits RVA23U64 + RVB23S64; adds Sha, Ssnpm; chain: RVA20S64 -> RVA22S64 -> RVB23S64 -> RVA23S64)", "scope_note": "This matrix lists only the S-mode/H-mode/M-mode-privileged extensions that RVA23S64 adds on top of RVA23U64. All RVA23U64 mandatory and optional extensions remain mandatory/optional here too - see the RVA23U64 tab for those. Sub-extensions implicitly required by a mandatory umbrella are omitted (per the U64 editorial policy): Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, Shcounterenw are subsumed under Sha (which requires H + Ssstateen + several Sh* sub-properties); Sha itself is the umbrella name and is represented here via its constituents H + Ssstateen.", "layer_definitions": { "none": "No new instructions. Platform property guarantee only - hardware must meet this constraint, but software (kernel, userspace) needs no changes.", "compiler": "Has ISA instructions that the compiler can auto-generate when -march enables the extension.", "kernel": "Requires kernel changes (typical for S-mode extensions: page table semantics, signal/trap handling, perf, timer, virt).", "userspace": "Requires userspace runtime library changes beyond what the compiler provides.", "full_stack": "Impacts the entire stack: kernel, compiler, and userspace libraries all need changes." } }, "mandatory": [ { "name": "Ss1p13", "long_name": "Supervisor Architecture v1.13", "description": "Supervisor-mode privilege architecture v1.13 (sret, sfence.vma; sstatus/sepc/scause/stval/stvec/sscratch/sie/sip/satp/senvcfg/scounteren CSRs). Supersedes Ss1p12.", "has_instructions": true, "csr_state": "new", "gcc_march": true, "gcc_status": "Implicit in privileged arch", "llvm_march": true, "llvm_status": "Implicit in privileged arch", "linux_kernel": true, "layer": "kernel", "layer_note": "Foundational privilege level. Linux runs in S-mode. Trap entry/exit, page table base (satp), interrupt delegation (mideleg/medeleg).", "rva23_new": false, "state_class": "csr-only", "state_class_basis": "Supervisor v1.13 baseline CSRs: sstatus, sie, stvec, sscratch, sepc, scause, stval, sip, satp, scounteren, senvcfg (Priv Arch §10)" }, { "name": "H", "long_name": "Hypervisor Extension", "description": "Hypervisor support: VS/VU virtualization modes, two-stage translation, hypervisor CSRs and instructions", "has_instructions": true, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Mandatory in RVA23S64 via the Sha umbrella. KVM-RISCV depends on H. Kernel: hypervisor state save/restore, two-stage translation (hgatp/G-stage), VS-mode timer/interrupts, hypervisor instructions (hfence.vvma/gvma, hlv/hsv, hinval.*). Userspace: VMM (QEMU, kvmtool) drives /dev/kvm ioctls; no direct H-instruction emission.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "Hypervisor CSRs: hstatus, hedeleg, hideleg, hvip, hip, hie, hgeip, hgeie, henvcfg, hcounteren, htval, htinst, hgatp, vsstatus/vsie/vstvec/vsscratch/vsepc/vscause/vstval/vsip/vsatp (Priv Arch §18)" }, { "name": "Ssstateen", "long_name": "State-Enable CSRs", "description": "sstateen0..3 / hstateen* / mstateen* CSRs gating lower-privilege access to extension state", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Gates U-mode and VU-mode access to other-extension state (Zcmt jvt, Sha CSRs, future extensions). Kernel must save/restore sstateen* across context switch and selectively grant userspace access. Required by Sha. Distros need this plumbed into the ptrace regset.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "{m,h,s}stateen0..3 CSRs (Smstateen/Ssstateen spec §3)" }, { "name": "Sscofpmf", "long_name": "Count-Overflow & Filtering for HPM", "description": "scountovf CSR + per-counter privilege filter (M/S/U/VS/VU inhibit) bits in mhpmeventN", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Linux perf subsystem reads scountovf to handle HPM counter overflow interrupts in S-mode (no SBI ecall hop). Per-counter privilege filtering (e.g., kernel-only sampling) drives mhpmevent inhibit bits. Userspace 'perf' tool consumes via perf_event_open syscall.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "scountovf CSR + mhpmevent.OF + sip/sie.LCOFIP bits (Sscofpmf spec)" }, { "name": "Sstc", "long_name": "Supervisor Timer Compare", "description": "stimecmp / vstimecmp CSRs for direct supervisor-mode timer programming", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Replaces sbi_set_timer ECALL with direct stimecmp CSR write. Linux already gates on RISCV_ISA_SSTC and falls back to SBI when unavailable. Significant timer-IRQ latency win and boot-path simplification. VS-mode mirror vstimecmp benefits KVM-RISCV guests.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "stimecmp / vstimecmp + menvcfg.STCE / henvcfg.STCE (Sstc spec)" }, { "name": "Ssnpm", "long_name": "S-mode Pointer Masking", "description": "Pointer masking CSR control at S-mode (senvcfg.PMM, henvcfg.PMM for VS)", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Kernel side of the U-mode pointer-masking feature (the Supm announcement in RVA23U64). Kernel configures senvcfg.PMM to set PMLEN, handles the prctl(PR_SET_TAGGED_ADDR_CTRL) opt-in, preserves PMLEN across context switch, and exposes it to ptrace.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "senvcfg.PMM / henvcfg.PMM (Ss-pointer-masking spec)" }, { "name": "Svinval", "long_name": "Fine-Grained TLB Invalidation", "description": "SFENCE.W.INVAL / SFENCE.INVAL.IR / SINVAL.VMA / HINVAL.VVMA / HINVAL.GVMA", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Decouples TLB invalidation from the ordering fence. Lets the kernel batch invalidations across many addresses and emit a single ordering fence at the end. arch/riscv flush_tlb_* paths use it when available.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Svinval — sfence.inval.ir/.w and hinval.* instructions, no new CSR" }, { "name": "Svnapot", "long_name": "NAPOT Page Table Entries", "description": "Naturally-Aligned-Power-of-Two PTE encoding for 64-KiB contiguous mappings", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "PTE-format extension: a single PTE can describe a 64-KiB naturally-aligned contiguous mapping (saves TLB pressure without changing the page table tree). Kernel hugetlb (CONFIG_RISCV_ISA_SVNAPOT) and transparent contiguous pages use it. Userspace sees it via mmap(MAP_HUGETLB).", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (PTE encoding feature, no new CSR)" }, { "name": "Svpbmt", "long_name": "Page-Based Memory Types", "description": "PBMT field in PTE selects memory attributes (PMA, NC, IO)", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "PTE bits 62-61 select PMA (default), NC (non-cacheable), or IO (I/O ordering). Kernel: ioremap, pgprot_noncached, pgprot_writecombine, DMA mappings drive PBMT directly instead of region-based PMA. Removes the need for vendor-specific memtype hacks.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (PTE bits 62:61 reused for memory type; menvcfg.PBMTE gates)" }, { "name": "Sv39", "long_name": "Sv39 Page Tables", "description": "39-bit virtual addressing with a 3-level page table", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "The mandatory minimum address-space size for RVA23S64. Sv48 / Sv57 are optional. Kernel page table walker, VM layout, KASLR, and direct map are all sized around Sv39 as a baseline.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (satp.MODE value 8 — capability advertised, field part of S baseline)" }, { "name": "Zifencei", "long_name": "Instruction-Fetch Fence", "description": "FENCE.I instruction for synchronizing instruction fetches with writes to instruction memory", "has_instructions": true, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Kernel uses for module loading, kprobes, eBPF JIT, ftrace. FENCE.I only synchronizes the issuing hart so kernel multi-hart icache flushes also use SBI / IPI. Userspace JIT (V8, JVM) should use the __riscv_flush_icache vDSO / syscall rather than FENCE.I directly.", "rva23_new": false, "state_class": "insn-only", "state_class_basis": "Zifencei — fence.i instruction, no new state" }, { "name": "Svade", "long_name": "Hardware A/D Bit Update", "description": "Hardware updates PTE Accessed and Dirty bits transparently", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Profile property: hardware must update PTE.A on read/exec, PTE.D on write. Kernel can drop the software A/D update fallback. Svadu (optional) is the inverse - hardware that can be told to NOT update A/D.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (raise page fault on A/D set rather than HW update)" }, { "name": "Svbare", "long_name": "Bare Translation Mode", "description": "satp.MODE = Bare (no translation) must be supported", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "none", "layer_note": "Profile property: S-mode must be able to run with no virtual-memory translation (Bare). Software-transparent guarantee that early boot and identity-mapped paths work before MMU enable.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (satp.MODE value 0 — bare/no-translation capability)" } ], "optional": [ { "name": "Sv48", "long_name": "Sv48 Page Tables", "description": "48-bit virtual addressing with a 4-level page table", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "Larger virtual address space. Kernel selects at boot via DT/ACPI (PAGE_TABLE_LEVELS=4) and starts in Sv48 when available, falling back to Sv39 otherwise.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (satp.MODE value 9 — 48-bit virtual addressing capability)" }, { "name": "Sv57", "long_name": "Sv57 Page Tables", "description": "57-bit virtual addressing with a 5-level page table", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": true, "layer": "kernel", "layer_note": "Even larger virtual address space (mirrors x86-64 LA57). Kernel runtime-detects via satp probe and starts in Sv57 when supported.", "rva23_new": false, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (satp.MODE value 10 — 57-bit virtual addressing capability)" }, { "name": "Svadu", "long_name": "Software A/D Bit Disable", "description": "Lets software opt out of hardware A/D bit update via menvcfg.ADUE", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "kernel", "layer_note": "Inverse of Svade: if implemented, software can write menvcfg.ADUE=0 to suppress hardware A/D update and handle it in the fault path. Rarely useful (real-time / QoS configurations).", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (HW A/D-bit update behavior; menvcfg.ADUE gates)" }, { "name": "Svvptc", "long_name": "Virtually-Tagged Page Table Cache", "description": "Implementation may cache PTEs by virtual address without the usual SFENCE.VMA requirements", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": false, "layer": "none", "layer_note": "Microarchitectural optimization. Software-transparent: kernel can drop a few redundant SFENCE.VMA calls in the transient case, but is not required to.", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (PTE-stale invalidation rule)" }, { "name": "Sdtrig", "long_name": "Debug Trigger Module", "description": "Hardware triggers for breakpoints, watchpoints, and ICOUNT", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": false, "layer": "none", "layer_note": "Debug infrastructure: hardware breakpoints/watchpoints/ICOUNT exposed through the Debug Module. Consumed by external debuggers (gdb via OpenOCD) and self-hosted kgdb; not part of Linux's normal ABI.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "tselect, tdata1..3, tinfo, tcontrol, mcontext, scontext (Debug spec §5)" }, { "name": "Sspm", "long_name": "S-mode Pointer Masking Facility", "description": "Pointer masking available *to* S-mode (the kernel itself)", "has_instructions": false, "csr_state": "bits", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": false, "layer": "kernel", "layer_note": "Parallel to Supm (U-mode) - announces that the kernel itself can use pointer masking. Few in-kernel consumers exist yet; potential KASAN-style tagged allocator integration.", "rva23_new": true, "state_class": "csr-only", "state_class_basis": "Supervisor pointer masking — uses {m,h,s}envcfg.PMM (Sspm spec)" }, { "name": "Ssstrict", "long_name": "Strict Execution Mode", "description": "Implementation strictly raises illegal-instruction on any unratified or unallocated opcode", "has_instructions": false, "csr_state": "none", "gcc_march": true, "gcc_status": "Supported (profile property)", "llvm_march": true, "llvm_status": "Supported (profile property)", "linux_kernel": false, "layer": "none", "layer_note": "Software-transparent profile property guaranteeing the implementation does not silently execute custom or unratified opcodes. Useful for compliance / sandboxing claims.", "rva23_new": true, "state_class": "property", "state_class_basis": "Named-feature / capability extension — adds no instructions and no state; pure discoverable property (conformance policy — no non-standard extensions / reserved encodings)" }, { "name": "Zkr", "long_name": "Entropy Source CSR", "description": "'seed' CSR providing access to a hardware entropy source", "has_instructions": false, "csr_state": "new", "gcc_march": true, "gcc_status": "Supported", "llvm_march": true, "llvm_status": "Supported", "linux_kernel": true, "layer": "userspace", "layer_note": "Hardware entropy via CSR read of 'seed'. Kernel RNG (random.c) can seed from it; getrandom() / /dev/urandom paths benefit. Userspace can also read directly when permitted (controlled via mseccfg / sstateen).", "rva23_new": false, "state_class": "csr-only", "state_class_basis": "seed CSR (Scalar Crypto §4 — Entropy Source)" } ], "summary": { "mandatory_count": 13, "optional_count": 8, "scope": "S-mode/H-mode additions on top of RVA23U64", "by_layer": { "none": "Platform property or NOP - software-transparent", "compiler": "Compiler auto-generates - march enables, no other changes", "kernel": "Kernel adaptation needed - userspace largely transparent", "userspace": "Userspace libraries (glibc, OpenSSL) need adaptation", "full_stack": "Kernel + compiler + userspace libraries all need work" } } }