K1 SPL Boot Flow — Four Entities & Relationships
① Build Artifacts (Host)
u-boot-spl-ddr.bin
SPL code + ddr_fw.bin (binman packed)
FSBL.bin
Signed boot image
build_binary_file.py
② K1 SoC (On-chip)
BootROM
128KB
③ SRAM (On-chip, 256KB, available at power-on)
SPL Code (.text)
0xC080,1000 ~ max 204KB
ddr_fw (embedded in image)
binman_sym offset locating
DDR FW Execution Area
0xC082,D000
memcpy
BSS / Stack
gd / heap
→ 0xC084,0000
DDR Controller
4 AXI ports · LPDDR3/4 · DFC
ddr_init(0xC000,0000, cs, rate, puts)
Load FSBL
Function pointer call
ddr_init()
USB fastboot /
SPI NOR etc.
④ DDR Memory Chip (External to SoC)
LPDDR4X · max 16GB · CPU view: low 2GB @ 0x0, high @ 0x1,0000,0000
BPI-F3: 2GB (memory@0, reg = <0 0 0 0x8000,0000>)
DDR training
Read/write training + 2400MT/s
Verify: write 0xAA55,AA55 → read back
Legend
① Build Artifacts (Host PC)
② K1 SoC (On-chip Logic)
③ SRAM (On-chip Memory)
④ DDR Chip (External on Board)
Cross-entity transfer
Intra-SRAM relocation
K1 CPU View — Physical Address Space Layout
0x0000,0000
DRAM Low Segment (0 ~ 2GB)
0x0000,0000
SDRAM_BASE
0x0020,0000
SYS_LOAD_ADDR — U-Boot proper load address
0x0100,0000
INIT_SP — U-Boot proper initial stack (16MB)
DDR verify address (write 0xAA55,AA55)
BPI-F3: entire 2GB DDR falls in this segment
0x8000,0000
Device IO Space (2 ~ 4GB)
0xC000,0000
ddrc Register Region (0x4280)
ddr_init() first parameter · exact usage determined by blob
0xC080,0000
SRAM (256KB, shared by Main CPU + Real CPU)
0xC080,1000
SPL code (.text, 204KB max)
0xC082,D000
DDR FW Execution Area
0xC083,7000
BSS (8KB)
0xC083,9000
Stack / gd
0xC083,B000
heap (20KB)
0xC084,0000
SPL_STACK (initial SP)
↑ Allocation direction: heap → gd → stack
↑ DDR FW at end of code area, memcpy here to execute
0xD400,0000+
Peripheral Registers
UART, I2C, Clock, GPIO, PMIC...
...
0x1,0000,0000
DRAM High Segment (4 ~ 18GB)
Maps to physical DRAM 2 ~ 16GB
BPI-F3 has only 2GB DDR, this segment unused
K1 supports up to 16GB DDR
0x4,8000,0000
DRAM split by Device IO into two segments: low 2GB (0x0) + high 14GB (0x1,0000,0000)
Different bus masters have different addressing capability (USB 2GB / GPU 16GB / PCIe 16GB / DMA 16GB)
Data source: K1x DDR memory space mapping doc (SpacemiT) + defconfig + DTS